This study presents a mathematical approach to distribute portable excess speed detectors in urban transportation networks. This type of sensor is studied to be located in a network in order to separate most of the demand node pairs in the system resembling the well-known traffic sensor surveillance problem. However, newly, the locations are permitted to be changed introducing the dynamic form of the sensor location problem. The problem is formulated mathematically into three different location problems, namely SLP1, SLP2, and SLP3. The aim is to find the optimal number of sensors to intercept most of the daily traffic for each model objective. The proposed formulations are proven to be an NP-hard problem, and then heuristics are called for the solution. The methodology is applied to AL Riyadh city as a real case study network with 240 demand node pairs and 124 two-way streets. In the SLP1, all the demand node pairs are covered by 19% of the network’s roads, whereas SLP2 model shows the best locations for each assumed budget of sensors to purchase. The SLP2 solutions range from 24 sensors with 100% paths coverage to 1 sensor with nearly 20% of paths coverage. The SLP3 model manages to redistribute the sensors in the network while maintaining its traffic coverage efficiency. Four locations structures manage to cover all the network streets with coverage ranges between 100% and 60%. The results show the capability of providing satisfactory solutions with reasonable computing burden.

In this study, we present exact and heuristics algorithms for a traffic sensors location problem called the screen line problem. It is a problem of how to locate traffic sensors on a transportation network where all the origin/destination node pairs are fully separated. The problem experiences two main complexity dimensions that obstruct finding an efficient solution algorithm for large-scale networks: its mathematical formulation, which is proved in the literature to be NP-hard, and an inherent combinatorial complexity due to the need for a network complete path enumeration. In this study, the problem is reformulated as a set covering problem. Thereafter, the dual formulation is recalled showing that the shortest path-based column generation method would yield as many paths as necessary and hence circumvent the intractability of the full path enumeration task. This path generation technique enables applying both the proposed heuristics and exact methods to the problem. In addition, the gap value between the heuristics and the exact algorithms is set to be examined statistically. For evaluation, three networks of different sizes were used to track the scalability of proposed algorithms. The methodology showed high efficiency to deal with up to 10,000 demand node pairs in addition to the capability of producing practical solutions with respect to normal traffic flow conditions. The proposed heuristics algorithm stipulates a gap value of less than 25% with more than 99% confidence.

Recently, Wireless Body Area Network (WBAN) has revolutionized e-health-care. WBAN boosts monitoring vital signs utilizing tiny wireless sensors implanted in or around the human body. In February 2012, the IEEE 802.15.6 WBAN standard was released for low-power and short-range communication around the human body. The standard defines one medium access control layer and three different physical layers: narrow band , ultra-wideband, and Human Body Communication (HBC) layers. We are motivated by exploiting the human body as a communication medium. We propose a novel optimized architecture for the HBC baseband transceiver based on deep learning. The receiver utilizes two deep neural networks: one for frame synchronization to recover data and timing precisely and the other for the channel decoder to improve transceiver performance and reduce power consumption. In addition, low-complexity Preamble/SFD generator, Walsh modulation, and FSC spreader modules are proposed to reduce the power consumption while preserving the transceiver performance. Compared with the traditional hard-decision channel decoder, the proposed neural network decoder improves the block error rate by 2 dB. The proposed HBC transceiver supports 1.312 Mbps data rate at 42 MHz clock rate. The transceiver is implemented in RTL and synthesized on 90 nm CMOS technology. It consumes 493 pJ/bit on the receiver side and 105 pJ/bit on the transmitter side.