This paper demonstrates a new technique to reduce the comparator delay dispersion caused by variable input overdrive. In the proposed technique, the conventional comparator circuit is modified by adding a variable driving-current block (VDCB) which is used such that it supplies the output node of the differential amplifier with a current that is inversely proportional with the level of input signal. Therefore the overdrive- caused delay dispersion is effectively reduced. The technique incurs small area overhead (only three transistors) compared with the previous works. The proposed circuit is implemented in 45nm technology. The effect of process variation on the performance of the proposed technique is studied by simulation. The results show that the overdrive-related propagation delay dispersion of the proposed technique is 26% of its counterpart in the conventional comparator for an input frequency up to 500MHz. The power consumption is 220 ?W at 200MHz.

This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of −19dBm for a BER= 10−12. The transimpedance amplifier achieves a transimpedance gain of 47dBΩ, 8GHz bandwidth with 0.45pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002mm2 whereas the complete optical receiver occupies a chip area of 0.16mm2. The power consumption of the TIA is only 2mW and the complete chip dissipates 16mW for a 1.1V single supply voltage. The complete optical receiver has a 58dBΩ transimpedance gain and 7GHz bandwidth.