A switched-capacitor delay line with self-equalizing sample-and-hold

Research Abstract
A simple SC delay line using a three-phase clock is described. The new circuit uses a reduced number of op amps. A circuit for correcting the amplitude deviation arising from the sample-and-hold effect is used. Unlike previous circuits this circuit does not affect the group-delay of the delay line. An example for a 10 µs delay line in the frequency range 0 to 250 kHz is given.
Research Authors
M.M. Doss and R. Unbehauen,
Research Department
Electrical Engineering Department
Research Journal
International Journal of Electronics
Research Member
Magdy Mofid Doss
Research Pages
pp. 929-933
Research Rank
1
Research Vol
vol. 64, No. 6
Research Year
1988

Safe limits against lateral stability of R.C. slender beams cast of normal, high and ultra high performance concrete

Research Authors
F. Kaiser
Research Department
Civil Engineering Department
Research Journal
Published in the international conference held in university of Dundee, U.K.,
Research Member
Fayez Kaiser Abdel-Sayed Ibrahim
Research Rank
3
Research Year
2002

Evaluation of using conventional analytical methods for the design of folded plates through comprehensive 3-dimensional analysis

Research Authors
F. Kaiser
Research Department
Civil Engineering Department
Research Journal
Published in Journal of Engineering sciences JES, Faculty of Engineering Assiut university
Research Member
Fayez Kaiser Abdel-Sayed Ibrahim
Research Rank
2
Research Year
2006
Subscribe to