This paper presents a lightweight hybrid random number generator (HRNG), implemented and evaluated on a Field-Programmable Gate Array (FPGA). The proposed design enhances security and randomness by synergizing jitter and metastability using a feedforward topology, which achieves a near-perfect Shannon entropy. Moreover, it is validated using three distinct entropy metrics, guaranteeing statistically robust random numbers for security-sensitive applications. In addition to entropy evaluations, this design is also rigorously analyzed using multiple industry-standard randomness test suites. Beyond the FPGA implementation, this work presents performance metrics, including area utilization, power consumption, maximum frequency, and energy usage per random bit, which are synthesized across three different technology nodes in Synopsys Design Compiler (SDC). All of the results from the FPGA and the …