A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Research Abstract
NULL
Research Authors
Said, Mostafa; Shalaby, Ahmed; Mehdipour, Farhad; Biglari-Abhari, Morteza; El-Sayed, Mohamed
Research Department
Electrical Engineering Department
Research Journal
Microprocessors and Microsystems
Research Member
Mostafa Said Sayed Abdelrehim
Research Pages
p 26-46
Research Publisher
NULL
Research Rank
1
Research Vol
v 43
Research Website
NULL
Research Year
2016