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An efficient neural cell architecture for spiking neural networks

Research Abstract

Neurons in a Spiking Neural Network (SNN) communicate using electrical pulses or spikes. They fire or trigger conditionally, and learning is sensitive to such triggers' timing and duration. The Leaky Integrate and Fire (LIF) model is the most widely used SNN neuron model. Most existing LIF-based neurons use a fixed spike frequency, which prevents them from attaining near-optimal accuracy. A research challenge is to design energy and area-efficient SNN neural cells that provide high learning accuracy and are scalable. Recently, the idea of tuning the spiking pulses in SNN was proposed and found promising. This work builds on the pulse-tuning idea by proposing an area and energy-efficient, stable, and reconfigurable SNN cell that generates spikes and reconfigures its pulse width to achieve near-optimal learning. It auto-adapts spike rate and duration to attain near-optimal accuracies for various SNN applications. The …

Research Authors
Kasem Khalil, Ashok Kumar, Magdy Bayoumi
Research Date
Research Department
Research Journal
IEEE Open Journal of the Computer Society
Research Member
Research Website
https://ieeexplore.ieee.org/abstract/document/10972324
Research Year
2025

A Lightweight Hybrid Random Number Generator With Dynamic Entropy Injection

Research Abstract

This paper presents a lightweight hybrid random number generator (HRNG), implemented and evaluated on a Field-Programmable Gate Array (FPGA). The proposed design enhances security and randomness by synergizing jitter and metastability using a feedforward topology, which achieves a near-perfect Shannon entropy. Moreover, it is validated using three distinct entropy metrics, guaranteeing statistically robust random numbers for security-sensitive applications. In addition to entropy evaluations, this design is also rigorously analyzed using multiple industry-standard randomness test suites. Beyond the FPGA implementation, this work presents performance metrics, including area utilization, power consumption, maximum frequency, and energy usage per random bit, which are synthesized across three different technology nodes in Synopsys Design Compiler (SDC). All of the results from the FPGA and the …

Research Authors
Sonia Akter, Shelby Williams, Prosen Kirtonia, Magdy Bayoumi, Kasem Khalil
Research Date
Research Department
Research Journal
IEEE Open Journal of Circuits and Systems
Research Member
Research Website
https://ieeexplore.ieee.org/abstract/document/11106931
Research Year
2025

Security and Privacy Solutions in Intelligent Transportation Systems: A Survey

Research Abstract

In recent years, the automotive industry has experienced a digital revolution, with vehicles increasingly equipped with computer systems, transitioning from purely mechanical machines to sophisticated autonomous entities. This evolution extends beyond individual vehicles to encompass Intelligent Transportation Systems (ITS), fundamentally altering transportation networks. While these advancements promise enhanced efficiency, safety, and travel experience, they also introduce new challenges, particularly in security and privacy. For example, AI-based systems are now used for real-time congestion prediction, allowing for optimized traffic flow; and predictive car maintenance, minimizing breakdowns and enhancing safety. However, these systems can be vulnerable to cyberattacks and data breaches. Integrating diverse technologies into transportation systems offers undeniable benefits, but it also has …

Research Authors
Ujunwa Madububambachu, Rabeea Fatima, Ahmed Sherif, Kasem Khalil
Research Date
Research Department
Research Journal
Internet of Things
Research Member
Research Website
https://www.sciencedirect.com/science/article/pii/S2542660525003269
Research Year
2025

S²rnn: Self-supervised reconfigurable neural network hardware accelerator for machine learning applications

Research Abstract

Hardware implementation of neural networks (NNs) is challenging due to varying application requirements. This often necessitates creating specific field programmable gate arrays (FPGAs) configurations from scratch for each application. This article proposes a flexible, self-supervised reconfigurable method to fit several application requirements by providing only the maximum available computational nodes a priori. The proposed method dynamically reconfigures the required number of hidden layers and nodes based on the application. The goal is to automatically determine the optimal NN configuration through reconfigurability to achieve maximum accuracy. Optimality is demonstrated through minimum average power, average delay, and area overhead, as well as maximum throughput and accuracy. Experimental results show that the proposed approach significantly reduces the optimized architecture search …

Research Authors
Kasem Khalil, Bappaditya Dey, Magdy Bayoumi
Research Date
Research Department
Research Journal
IEEE Internet of Things Journal
Research Member
Research Website
https://ieeexplore.ieee.org/abstract/document/10742088
Research Year
2025
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